In the fabrication of integrated circuits, a number of well established processes involve the application of ion beams to semiconductor wafers in vacuum. These processes include, for example, ion implantation, ion beam milling and reactive ion etching. In each instance, a beam of ions is generated in a source and is accelerated toward a target wafer.
Ion implantation has become a standard technique for introducing dopant materials into semiconductor wafers. A desired dopant material is ionized in an ion source, the ions are accelerated to form an ion beam of prescribed energy and the ion beam is directed at the surface of the wafer. The energetic ions in the beam penetrate into the bulk of the semiconductor material and are embedded into the crystalline lattice of the semiconductor material to form a region of desired conductivity.
The target mounting site is a critical component of an ion implantation system or other ion beam system. The target mounting site is required to firmly clamp a semiconductor wafer to a platen for ion implantation and, in most cases, to provide cooling of the wafer. In addition, a wafer handling system is provided for loading wafers onto the target mounting site and for removing the wafers after completion of ion implantation.
Cooling of wafers is particularly important in commercial semiconductor processing wherein a major objective is to achieve a high throughput in terms of wafers processed per unit time. One way to achieve high throughput is to use a high current ion beam so that the implantation process is completed in a relatively short time. However, large amounts of heat are likely to be generated by the high current ion beam. The heat can result in uncontrolled diffusion of impurities beyond described limits in the wafer and in degradation of patterned photoresist layers. It is usually necessary to provide wafer cooling in order to limit the maximum wafer temperature to about 100° C.
A number of techniques for clamping a semiconductor wafer at the target mounting site are known in the art. According to one well-known technique, the wafer is clamped against a platen by a peripheral clamping ring which engages the outer periphery of the front surface of the wafer. The front surface of the wafer, with the exception of the area blocked by the clamping ring, is exposed for ion implantation.
A wafer clamping technique which eliminates the requirement for a peripheral clamping ring and which permits the use of a flat platen surface is centrifugal clamping. In centrifugal clamping, the wafer mounting site is rotated about an axis of rotation. The platen surface is oriented at an angle with respect to the axis of rotation so that centrifugal force presses the wafer against the platen surface. However, the requirement for rotating the wafer mounting site in order to provide centrifugal clamping adds complexity and is not always practical.
Another known technique for clamping semiconductor wafers involves the use of electrostatic forces. A dielectric layer is positioned between a semiconductor wafer and a conductive support plate. A voltage is applied between the semiconductor wafer and the support plate, and the wafer is clamped against the dielectric layer by electrostatic forces. Electrostatic wafer clamps are disclosed, for example, in U.S. Pat. No. 5,452,177 issued Sep. 19, 1995 to Frutiger and U.S. Pat. No. 5,969,934 issued Oct. 19, 1999 to Larsen.
Regardless of the clamping technique utilized, thermal transfer from a semiconductor wafer to a heat sink in vacuum is problematic. Heat transfer by radiation from the wafer is inadequate, except for low current ion beams. Even where the wafer is in physical contact with the platen surface, surface irregularities on the wafer and the platen surface limit actual contact to about 5% of the two surface areas and thereby limit solid-to-solid thermal conduction.
A variety of techniques have been disclosed for ensuring a high rate of thermal transfer from the wafer to a platen or heat sink. A contoured heat sink for optimizing conductive heat transfer between a wafer and a heat sink is disclosed in U.S. Pat. No. 4,535,835 issued Aug. 20, 1985 to Holden. The heat sink surface is contoured to impose a load that results in a uniform contact pressure distribution and a stress approaching the elastic limit of the wafer for a peripherally clamped wafer.
Another prior art technique for thermal transfer in vacuum involves the use of a thermally conductive polymer between a semiconductor wafer and a heat sink. A tacky, inert polymer film for providing thermal contact between a wafer and a heat sink is disclosed in U.S. Pat. No. 4,139,051 issued Feb. 13, 1979 to Jones et al. An automated wafer clamping mechanism utilizing a pliable, thermally-conductive layer between a semiconductor wafer and a heat sink is disclosed in U.S. Pat. No. 4,282,924 issued Aug. 11, 1981 to Faretra. The wafer is clamped at its periphery to a convexly curved platen having a layer of thermally-conductive silicone rubber on its surface. A thermal transfer technique which utilizes centrifugal clamping and a flat platen surface having a pliable, thermally-conductive polymer layer for effective thermal transfer is disclosed in U.S. Pat. No. 4,832,781 issued May 23, 1989 to Mears.
Prior art silicone rubber layers have been relatively thick. A disadvantage is that such materials are not inherently heat conductive. This can be compensated for by doping the material with heat conductive particles and/or by applying pressure to the wafer such that the number of contact points increases to compensate for the limited heat transfer at each point. The doping method has the disadvantage of adding an extra process step and the possibility of particle or elemental contamination by the heat conductive particles. The increased pressure method has the disadvantage that the increased pressure may induce wafer breakage, coupled with the difficulties of applying such pressure to the wafer. When the pressure is applied to the wafer edge, as with a mechanical clamp ring, the pressure at the center of the wafer is limited by wafer flexure. When the pressure is applied across the wafer, as with an electrostatic clamp, the disadvantages are the cost and difficulty of manufacturing a sufficiently powerful clamp, as well as the use of high voltages to achieve a given cooling capacity. In either method, the use of the flexible material, which is usually organic, gives rise to organic contamination, known to be detrimental in wafer processing.
The technique of gas conduction has also been utilized for wafer cooling in vacuum. Gas is introduced into a cavity or microscopic voids behind a semiconductor wafer and effects thermal coupling between the wafer and the heat sink. Gas-assisted, solid-to-solid thermal transfer with a semiconductor wafer is disclosed in U.S. Pat. No. 4,457,359 issued Jul. 3, 1984 to Holden.
The gas conduction technique has the disadvantage that the heat sink surface must be strictly controlled dimensionally to match the characteristic distances of molecular travel at the pressures of the cooling gases used. Further, leakage of the cooling gas is a problem, resulting in non-uniform cooling, and possible degradation of the process by localized gas concentrations at the leakage areas. For a given cooling capacity, the gas pressure may flex the wafer, again possibly degrading the integrity of the process.
As semiconductor device geometries become progressively smaller and wafer sizes become progressively larger, the allowable particulate contamination specifications become more restrictive. The particulate performance of wafer clamping mechanisms is of particular concern because the wafers physically contact the clamping surface. In the case of electrostatic wafer clamps, the electrostatic forces which are employed to clamp wafers also attract particles.
Accordingly, it is desirable to provide surface structures for contacting a workpiece which are characterized by low particle generation and low particulate contamination of the workpiece and which may be characterized by efficient thermal transfer from the workpiece.